1. Field of the Invention
The present invention relates to a method of making a semiconductor assembly, and more particularly to a method of making a thermally enhanced semiconductor assembly that includes a semiconductor device, a heat spreader, an adhesive and build-up circuitry.
2. Description of Related Art
The convergence of mobility, communication, and computing has created significant thermal, electrical and cost challenges to the semiconductor packaging industry. For instance, semiconductor devices are susceptible to performance degradation as well as short life span and immediate failure at high operating temperatures. Even though chip-level design is continuously reducing the operating bias voltage to get the benefit of reduced power, integrating more functions in a limited space often offsets this potential solution. In addition, semiconductor devices are often susceptible to undesirable electro-magnetic interference (EMI) or other inter-device interference when they are densely packed together. The signal integrity of these devices can be adversely affected when they perform high frequency transmitting or receiving. As such, providing a semiconductor assembly that can provide adequate thermal dissipation, optimize signal integrity, assure high reliability and maintain low cost manufacturing is highly desirable.
Packaging technologies such as plastic ball grid array (PBGA) packages, Quad-Flat No-Lead (QFN) packages, Wafer Level Package (WLP), and Fan-Out Wafer Level Package (FOWLP) have been developed extensively to meet these demands. Plastic ball grid array (PBGA) packages have a chip and an interconnect substrate enclosed in a plastic housing and are attached to a printed circuit board (PCB) by solder balls. The laminated substrate includes a dielectric layer that often includes fiberglass. The heat from the chip flows through the plastic housing and the dielectric layer to the solder balls and then the PCB. Since the plastic housing and the dielectric layer typically have low thermal conductivity, the PBGA provides poor heat dissipation.
Quad-Flat No-Lead (QFN) packages have the chip mounted on a copper die pad which is soldered to the PCB. The heat from the chip flows through the die pad to the PCB. However, since the wire-bonded I/O pads and lead frame type interposer have limited routing capability, the QFN package is not suitable for high performance, high input/output (I/O) devices.
Wafer-level packaging (WLP) or wafer-level chip-scale packaging (WL-CSP) is a packaging technology while semiconductor chips are still in wafer form. As the size of the wafer level package is the same as the chip itself, this packaging format is highly desirable for portable Applications. Wafer level packaging typically features build-up circuitry on the chip surface to transform the peripheral contact pads to wider and larger area-array terminals for assembly consideration. Since the build-up circuitry is formed directly on the chip surface and the fine routing lines allow for greater routing density, the signal integrity can be optimized. However, as the routing circuitry of wafer level packaging is strictly constrained by the silicon area of the semiconductor chip, wafer level packaging is not suitable for most high pin count devices.
U.S. Pat. No. 3,903,590 to Yokogawa discloses an assembly in which semiconductor chips are forcefully embedded in a metal substrate so that a supporting platform can be created. In this approach, a dielectric layer and a conductive trace are overlaid on the embedded chips and the metal substrate for electrically connecting the contact electrodes of the semiconductor chip. The heat flows from the chip through the metal substrate which also provides mechanical support for the fan-out routing circuitry. Although a supporting platform is created and thermal issues can be resolved, applying a pressure of about 370 kg/cm2 at a temperature of 100° C. to 200° C. to press the chip into the metal block is prohibitively cumbersome and prone to damage the chip. Furthermore, since it is difficult to accurately position the chip in the metal substrate due to lateral displacement, and there is no bonding material to secure the embedded chip, voids and inconsistent bond lines arise between the chip and the heat slug. As a result, the assembly suffers from high yield loss, poor reliability and excessive cost.
U.S. Pat. No. 5,111,278 to Eichelberger et al. discloses an assembly in which semiconductor chips are disposed on the planar surface of a substrate. One or more encapsulating/dielectric layers overlay the faces and sides of the chips before fabricating vias and interconnections through the encapsulant to the contact pads to connect these chips. The substrate can include glass, ceramic, plastic, silicon and composites, and the encapsulating layer can include thermoplastic and thermo-set materials. The heat from the chip flows through the encapsulating housing and the substrate to the ambient atmosphere or PCB. Since the plastic housing and the plastic materials typically have low thermal conductivity, this assembly provides poor heat dissipation. Furthermore, as semiconductor chips are placed on a planar surface before lamination, misplacement during die attachment and lamination-induced chip cracking during the build-up process often result in high yield loss.
U.S. Pat. No. 5,353,498 to Fillion et al., U.S. Pat. No. 6,154,366 to Ma et al., and U.S. Pat. No. 6,701,614 to Ding et al. disclose an assembly in which additional area is provided by the encapsulating material which encloses semiconductor chips to be positioned for integrated circuit module fabrication. In this approach, a chip is placed on a supporting film with contact pads facing the supporting film. As such, after molding material is added to the surroundings of the chip, these contact pads are co-planar with the encapsulating material. A dielectric layer having vias can be aligned with the contact pads and an electrical conductor extending through the vias is situated on the substrate. Since the molding material is typically a poor thermal conductor, the heat generated from the enclosed chip is blocked by the molding compound. Even though a mechanical grinding fixture can grind off the backside of the encapsulating material in order to re-expose the chip and therefore lower thermal resistance, the slow grinding process of removing the hardened molding compound can be expensive for high volume manufacture. Furthermore, since the interfacial surfaces between the chips and the encapsulating material would be exposed due to grinding off the backside encapsulating material, moisture penetration, voids and cracks at the interfaces can result in serious reliability concern.
U.S. Pat. No. 5,073,814 to Cole et al., U.S. Pat. No. 5,161,093 to Gorczyca et al., U.S. Pat. No. 5,432,677 to Mowatt et al., and U.S. Pat. No. 5,745,984 to Cole et al. disclose an assembly in which a semiconductor chip is housed in a recess area on the substrate surface before forming circuitry to interconnect the contact pads of the chip. Since the top surface of the chip can be co-planar with the surface of the substrate, lamination-induced displacement or chip cracking can be avoided. However, plastic substrates such as epoxy or polyimide have low thermal conductivity which limit heat dissipation, whereas dielectrics with higher thermal conductivity such as epoxy filled with ceramic or silicon carbide have low adhesion and are prohibitively expensive for high volume manufacture.
U.S. Pat. No. 7,929,313 to Ito et al. discloses a manufacturing method to form a metal layer on the inner wall surface of a cavity so that the embedded semiconductor chip can be protected from electro-magnetic interference. Like other cavity type approaches, this approach suffers poor manufacturing throughput due to inconsistent cavity formation in the resin. Furthermore, since the metal is deposited in the cavity by electro-plating, it has limited thickness and does little to improve the package's thermal performance.
U.S. Pat. No. 6,555,906 to Towel et al, and U.S. Pat. No. 6,750,397 to Ou et al. disclose an assembly in which a semiconductor chip is housed in a cavity of a heat spreader such as a metal block. Since the cavity in the metal block is formed by etching or by micro-machining or by milling out a portion of the material, the major drawbacks include low yield and high cost. Furthermore, inconsistent cavity depth control of the recess in the metal block results in low throughput and low yield in volume production.
In view of the various development stages and limitations in currently available packages for high power and high performance semiconductor devices, there is a need for a semiconductor assembly that is cost effective, reliable, manufacturable, versatile, provides good signal integrity and has excellent heat spreading and dissipation.